Higher packing densities of integrated circuit devices is generally realized by reducing individual component size and correspondingly reducing junction depths and other dimensions of the component elements. When scaling down FETs, the junction depth must be made very shallow in order to prevent the undesirable occurrence of the well known punch-through phenomenon. Because of this scaling down of the dimensions of the various component elements, the resistance and/or sheet resistance of these elements is increased. This creates a serious problem with relatively narrow shallow doped regions such as the source and drain regions of MOS field effect transistors (MOSFETs) in that it is difficult to use these regions for interconnections and the high series resistance of the source and drain will reduce drive current thereby degrading device performance.
One solution to this problem is siliciding of the surfaces of the source and drain regions to reduce their electrical resistance. Such a solution is disclosed in U.S. Pat. No. 4,384,301 which issued May 17, 1983 to Tasch, Jr. et al. Tasch shows a MOSFET wherein the contact surfaces of the source and drain comprise metal silicide. However, such a structure is not without problems too.
The contact resistance between any refractory metal or its silicide and the doped silicon is strongly dependent upon the concentration of doping at the silicide to silicon interface. Typically, in order to obtain a contact having small resistance, the silicon at the interface must have a doping concentration of about 10.sup.20 atoms per cm.sup.3. It is virtually impossible to fabricate very shallow source and drain regions having such a high doping level.